1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (DRAM) for driving a memory cell array by using a row address strobe signal.
2. Background Information
Advances in semiconductor memory fabrication have significantly increased the degree of integration thereof. High speed access of the data within semiconductor memory has become strongly demanded. The data access is controlled by a central processing unit (CPU). Generally, in a DRAM, a data access operation is performed by synchronizing with a system clock generated in the system, i.e. external clock. As the clock speed of the system clock is increased, the data access speed of the DRAM chip should be increased to a speed corresponding to the speed of the system clock. It is not uncommon for a system clock to operate at 66 MHz (which means that a pulse period of the system clock is nano-seconds (ns)), and this will be increased in the future. The data access operation of the chip must be performed with a speed corresponding to the system clock speed. However, the data access operation of a contemporary semiconductor memory device can not keep up with the processing speed of current systems.
FIG. 1 shows the layout of a general DRAM chip. An array construction of FIG. 1 is divided into four memory arrays each having a number of sub-arrays Moreover, the array construction may be changed according to the degree of integration of the chip. Data in each sub-array is accessed by the system control signals. The control signals are executed through pins in the exterior of the array.
FIG. 2 is a diagram showing the connection pins of FIG. 1. A TTL (transistor-transistor logic circuit) level row address strobe signal RAS and a column address strobe signal CAS are controlled by the CPU of the system. It should be noted that the row address strobe signal RAS is connected to only one pin.
FIG. 3 is a block diagram illustrating a conventional data access circuit. A control & clock part 40 receives active low signals RAS, CAS and W from the chip exterior and outputs signals to a data input buffer 10, a sense amplifier & input/output gate 70, a data output buffer 80, a column decoder 60, an address counter 50, a row decoder 30 and an address buffer 20. The data input buffer 10 receives signals from the control & clock part 40 and signals DQ1-DQ4 from the chip exterior and outputs signals to the sense amplifier & input/output gate 70 as well as signals DQ1-DQ4 to the exterior of the chip. The address counter 50 receives a signal from the control & clock part 40 and outputs a signal to the row decoder 30. The data output buffer 80 receives a signal from the control & clock part 40, the sense amplifier & input/output gate 70 and signals DQ1-DQ4 from the chip exterior and outputs signals to the sense amplifier & input/output gate 70 and signals DQ1-DQ4 to the chip exterior. The column decoder 60 receives signals from the control & clock part 40 and the address buffer 20 and outputs signals to the sense amplifier & input/output gate 70. The address buffer receives address signals A0-A9 from the chip exterior, signals from the control & clock part 40 and the address counter 50 and outputs signals to the column decoder 60 and to the row decoder 30. The memory array receives signals from the row decoder 30 and the sense amplifier & input/output gate 70 and outputs signals to the sense amplifier & input/output gate 70.
In the construction of the DRAM shown in FIG. 1, a number of sub-arrays having a number of accessible memory cells with multiple rows and columns are provided depending on the integrated degree of the chip. In FIG. 3, a memory array 100 includes one sub-array or more. In the case of 4 Megabit DRAM, 16 megabit DRAM or more highly integrated semiconductor memory device, usually a number of sub-arrays are arranged within the memory array 100. In addition, a sense amplifier and a data line, etc. are separately provided and a buffer for simultaneously generating data to the exterior of the chip is provided. The operation of the circuit shown in FIG. 3 is described by way of a nibble mode example. The nibble mode is an operating cycle performing a page mode cycle at high speed in the operating mode of the DRAM. In the page mode a column address is not applied from the exterior, but incremented in the interior of the DRAM device.
An example of the timing of a nibble mode operation is shown in FIG. 4. The nibble mode is identical to the page mode except that a column address is not strobed, and the parts which are not strobed can be repeated at high speed. In the case of 16 megabit DRAM, an accessible memory cell with the nibble mode cycle is data of 4 bits. In FIG. 3, one row address strobe RAS, one column address strobe signal CAS, and a number of address lines A0 to A9 control the access of data respectively. A number of sub-arrays are activated when the row address strobe signal RAS goes to logic level "low" enabling the chip. Subsequently, data stored in the memory cell is read out to the exterior pins of the chip by a series of active cycles.
On the other hand, in order to read out new data having a different column address, a subsequent row address strobe signal RAS is set to logic level "high". Therefore, a data output chain is reset and a time interval t1 exists as shown in FIG. 4. Thereafter, the above-mentioned process is repeated by a logic level "low" row address strobe signal RAS. Thus, 4 bits of data are produced in response to the column address strobe signal RAS. While the row address strobe signal RAS is reset during the interval t1 (i.e. the signal RAS is precharged), output data is in a "don't care" state. After the signal RAS is activated 4 bits of data are produced.
In order to improve the performance of the system, a method for increasing the access speed of the DRAM, or another method for providing more random data during a given time should be implemented. However, methods for increasing the access speed have limitations given the current processes and design techniques. Further, the access speed of data is too slow with regards to the speeds of current CPUs. In the nibble mode, if a cycle time of the column address strobe signal CAS is 15 ns and that of the row address strobe signal RAS is 120 ns (in this case, a precharge time of the row address strobe signal RAS becomes 60 ns), data of 4 bits is produced during 60 ns and no data can be generated during the remaining 60 ns of the interval t1. Consequently, increases in the access speed of data has limitations, since data can not be generated during the precharge cycle.